This is a Scala-based digital hardware description language (HDL) that can generate VHDL/Verilog files compatible with mainstream EDA tools. Compared with traditional HDL, it not only has a more concise and powerful syntax but also fully integrates the object-oriented and functional programming features of Scala. During the compilation stage, it can automatically check common errors such as type bit width matching, cross-clock domain, and loop assignment, achieving an efficient and flexible hardware modeling and verification process.